Senior ASIC Design Engineer

Who We are
Synopsys technology is at the heart of innovations that are changing the way we live and work. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced tools for silicon chip design, verification, IP integration, and application security testing. Our technology helps customers innovate from Silicon to Software, so they can deliver Smart, Secure Everything.

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Come and be part of a collaborative team environment that innovates and develops the latest IP solutions that enable the way the world designs.  Join US!

Senior ASIC Design Engineer
You would be working as part of a highly experienced Digital Design Team, targeting the next generation DDR products. Strong theoretical and practical background in Memory System Architecture is an asset. You shall be working for synthesis for RTL Design and defining timing constraints. The position offers an excellent opportunity to work with an experienced team of digital design and verification engineers responsible for delivering next generation DDR PHY.

Qualifications

• Must have hands-on experience in RTL design (Verilog or System Verilog).
• Have experience in defining synthesis constraints and STA.
• Must have hands-on experience with multiple clock domain design.
• Have experience with CDC/RDC/LINT tools.
• Good organization and communication skills for interacting between different design groups and customer support teams.

Weightage:

• Knowledge of Perl/Shell scripts.

Educational background:

• BE/B.Tech/M.Tech OR equivalent with minimum 4-5 years industry experience.