R&D Engineering, Sr Staff Engineer

• Candidate will be part of platform team working for Static Verification tools over SpyGlass and VC Platform
• Design, develop, troubleshoot the core static algorithms.
• Design and develop standard and customized features / checks using platform technologies for inference, propagation and verification.
• Will be working with other local and global teams.
• Design and development of state of the art EDA tools involving development of new and innovative algorithms.
• Create Verilog and VHDL test cases to test the developed feature.

Skills Required

• Ability to develop new software architecture and good leadership skills.
• Fluent in C/C++ with extensive work experience in data-structures and algorithms.
• Excellent algorithm analysis skills and a good knowledge of data structures.
• Good knowledge of Tcl and Perl-based development on Unix.
• Good knowledge of Verilog, SystemVerilog & VHDL HDL.
• Familiarity with ASIC design flow and the EDA tools and methodologies used therein.
• Familiarity with multi-threaded and distributed code development.
• Self-motivation, self- discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success.
• Quality focus – one who believes in quality and wants to make a difference.
• Experience of production code development on Unix/Linux platforms.