ASIC Digital Design Engr, II

At Synopsys, we’re at the heart of the innovations that change the way we work and play, Self-driving cars, Artificial Intelligence, The cloud, 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Selected candidate will be part of the DesignWare IP Verification R&D team at Synopsys. He/She will be expected to specify, design/architect and implement state-of-the-art Verification environments for the DesignWare family of synthesizable cores and perform Verification tasks for the IP cores. Candidate will work closely with RTL designers and be part of a global team of experienced Verification Engineers.

Job role will have a combination of Test planning, Test environment coding both at unit level and system level, Test case coding and debugging, FC coding and review and meeting quality metric goals and regression management.

The candidate will be part of the Solutions Group, India. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in the Design & Directed Verification domain.

Key Qualification

• BS/MS in EE/EC with 4+ years of relevant experience in the verification of IP cores and/or SOC
• Must have proven experience in developing HVL (System Verilog/UVM) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage and Code coverage.
• Experience on memory interface protocols (DDR, LPDDR) is highly desirable.
• Exposure to IP design and verification processes including VIP development is an added advantage.
• Good communication skills, debug and problem-solving skills and should be self-motivated

Preferred Experience

• Be a technical contributor in the Verification Tasks – System Verilog/Verilog coding of testbenches, Test cases, performing verification tasks such as coverage, debug, regressions using the latest methodologies such as UVM, Formal verification etc.
• Creates deliverables which do not require close review or supervision by a Senior Technical Engineer
• Be able to study the coverage metrics and improve them with definition of additional test cases in directed environment, at least for small/ medium complexity features of the protocol/ product specs.
• Familiarity with HDLs such as Verilog and scripting languages such as shell/Perl/Python etc. is highly desirable.
• Works in a project and team-oriented environment with teams spread across multiple sites, worldwide.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.