ASIC Physical Design, Staff Engineer

Years of Exp : 5 - 9 yrs with valid B.tech/M.tech. 
 
Job Description

IR Signoff for High Performance Designs like DDR/LPDDR,UCIE,HBM and SOC.
Validating the PG Grid using Grid Resistance & Secondary PG Resistance Checks.
Validating the IR Drops using Static IR , Dynamic IR Vless & VCD Checks for validating Die & Pkg Components of IR Drops.
Working with SOC and Packaging Teams on Bumps Assignments / RDL Enablement /Pkg Routing Optimizations to improve overall PDN Design.
Signal EM & Power EM Signoff.
Strong Automation background in Python, Perl , TCL, Shell scripting.
Good to have hands on experience in Physical Design, STA and similar domains.
Good to have understanding on Package PDN analysis and routing.

Skill Set
Hands – on experience in PDN Signoff using Redhawk / RHSC / Voltus at block level / SOC Level.
Good understanding on Power Integrity Signoff Checks.
Proficient in scripting languages (Tcl and Python).
Familiarity with iccompiler for RDL / Bump Planning.
Ability to communicate effectively with multiple global cross-functional teams. Effective presentation skills.
Candidates with AE or Product development background will also be preferred.