FE Design Engineer

FE design engineer

Job Description & Requirements

Our Silicon Lifecycle Management (SLM) business is all about building next-generation intelligent in-chip sensors, hardware/software capabilities and analytics to integrate into technology products to manage and improve each semiconductor lifecycle stage. We offer the world’s first full hardware IP, test, and end-to-end analytics to help customers integrate faster, optimize performance/power/area/schedule/yield, and enhance reliability. Meeting the unique challenges posed by various target applications, SLM enables differentiated products to market quickly with reduced risk.

The Digital R&D team within the HDG (Hardware Development group) is chartered with developing digital hardware IP that are crucial component of the SLM sensors.

Job responsibilities include:

• Design and implement behavioral RTL models of advanced digital circuits.
• Responsible for RTL coding of blocks that go into the Sensor IP.
• Help in characterizing the IP and contribute in lab bring up.
• Work with Verification teams to verify functionality.

Preferred skills
 

• Good knowledge of Verilog and System Verilog with experience in behavioral and structural RTL coding.
• Basic knowledge of viewing and understanding circuit schematics.
• Candidates with good understanding and experience of PnR and DFT will be given preference.
• Python and TCL coding to setup front end flows is highly desirable.
• Experience with industry standard tools for formal verification is highly desirable.
• 3-5 years of industry experience is highly desirable.