Analog Design , Principal Engineer

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules

Mixed-signal Analog circuit design Expert / lead in PLL and SERDES design

We’re looking for an A&MS Senior Circuit Design Professional to join & lead PLL  design projects and build team.
Does this sound like a good role for you?

This role involves analyzing various mixed signal techniques for dynamic and static power reduction, performance enhancement and area reduction. You’d leverage your strong understanding of circuit simulation and circuit layout as well as knowledge of bipolar, CMOS, passive structure, and interconnect failure modes.

You will be joining an expanding analog/mixed-signal PLL team involved in design and development on cutting-edge area of High Speed PHYSICAL Interface Development.

You will develop Analog Full custom circuit macros, i.e., PLL, Clock Path Functions , and SERDES clocking solutions needed for High Speed PHY IP,  in planer and fin-fet CMOS technology..


You will build and manage key analog design talent as a team to grow business impact in execution of design projects and nurture problem solving skills.

You will be working with experienced set of teams locally and with people from various sites spread across globe.


Key Qualification:
BE +12 years of relevant experience / MTech +10 years of relevant experience in mixed signal analog , custom circuit design , >2years experience in leading & mentoring engineering teams , educational qualifications in Electrical/Electronics/VLSI Engineering or other relevant field of study.

Technical Attributes


Analog and Mixed Signal Design with focus on PLLs and clocking circuits.
Strong knowledge of RF architecture and blocks such as transceivers, VCOs, LNA and up/down converters. Good knowledge of ADC/DAC designs/architectures would be helpful too.
Design Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits.
Conduct high speed digital circuit design and timing/phase noise analysis.
Create behavioral models of PLL to drive architectural decisions and derive block-level requirements for analog and digital blocks.
Work closely with layout team to implement layout view of designs.
Construct lab and ATE test plans; review measurements/debug for characterization

Mandatory:

• Strong fundamentals of CMOS design, passive RC circuits, switched cap circuits.
• The various task involves, circuit design, validation, mixed signal validation, and reliability validation.
• Exposure to PLL designs (either Charge-Pump based or ADPLLs or both, Fractional-N PLLs, spread-spectrum PLLs, etc.) Familiarity Multi Gbps range High speed designs
• Good knowledge of control systems, band gaps, bias, op-amps, LDOs, feedback and compensation techniques.
• Experience in LC VCO/DCO design. Good exposure to performance parameters of VCO as well as complete PLL architecture. Exposure to High speed digital circuit design and analysis with timing and flow closure.
• Exposure to Digitally assisted analog circuit and techniques.
• Can micro architect circuit from specifications, can create simulation benches to verify the specification, can understand and debug circuit.
• Should have understanding of layout and parasitic extraction
• Hands-on experience with PLL top-to-bottom level spice and mixed mode design and simulation

 
Preferred:

• Familiarity with esd & latchup design verification in mixed signal analog design, crosstalk coupling impact on timings .
• Familiarity with automation / Scripting language and Matlab

 
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.