RTL Design and Signoff Engineer, Staff Engineer

At Synopsys, we are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we are powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation and SoC Design, we want to meet you.

Job Description and Requirements
The role is for RTL Design and Signoff of IP/Subsystem/SoC Design in the System Solutions Group (SSG). At SSG, we are a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, methodology to enable our customers complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies.

As part of this role, you can expect to develop and deliver your expertise in RTL Signoff and RTL Design Techniques while working on activities such as Lint/CDC/RDC Checks, Timing Constraints Development, Preliminary Synthesis, Formality and RTL Design. The role will expose you to various innovative technologies deployed for RTL Quality Signoff for Semiconductors.

Responsibilities

• Perform RTL Quality Signoff Checks such as LINT, CDC, RDC.
• Understand the design/architecture and develop timing constraints for synthesis and timing.
• Run preliminary synthesis to ensure that the design can be synthesized as intended.
• Run formality to ensure equivalence of RTL and gates.
• Integrate IPs in SoCs/Subsystems and create RTL design as per need of the customer.

Required

• B.E/B. Tech/M.E/M. Tech in electronics with 4-9 years’ experience in RTL Design and Verification.
• Hands-on experience on static verification tools such as Spyglass performing LINT, CDC, RDC.
• Good conceptual understanding of design/architecture pitfalls across clock/reset domain crossing.
• Good conceptual understanding of RTL rule checks.
• Hands-on experience on synthesis and timing constraints development.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.