Job Description:
FPGA group in Synopsys delivers a number of products such as Synplify Pro, Synplify Premier,
ProtoCompiler, Certify and Identify. These products are widely used in the industry for implementation
of FPGA designs, prototyping and debugging of ASICs using FPGAs. Logic synthesis software, which is
part of Synplify Pro and Synplify Premier products, is the industry standards for producing high-performance, cost-effective FPGA designs. Its unique Behavior Extracting Synthesis Technology® (BEST™)
performs optimization at a high level first, before synthesizing the RTL code into specific FPGA logic. This
approach allows for superior optimization across the FPGA, provides fast runtimes and support for very
large designs.
Looking for a R&D engineer in Synplify mapper R&D team in Bangalore for the following role and with
the given background/skill sets.
Roles and responsibility:
• A person in the position would be responsible for designing, developing, troubleshooting,
debugging and maintaining large and efficient software systems for technology mapping, logic
and timing optimization steps of the FPGA logic synthesis software.
• The person is expected to
structures and algorithms in C/C++.
o Work with CAE team in test planning, execution and customer support.
o Maintain and support existing product and features.
Expected background and skill:
The person is expected to have:
• 5+ years of experience in designing, developing and maintaining large EDA software.
• Sound knowledge in data structures, graph algorithms and C/C++ programming on
Windows/Unix.
• Familiarity in digital logic design.
• Familiarity with Verilog/VHDL RTL level designs, timing constrains, static timing analysis.
• Working knowledge of FPGA design tools and flows is a plus
Our Technology, Your Innovation
Synopsys is the leading silicon to systems design solutions company. Synopsys accelerates technology innovation, from silicon to systems.
Synopsys delivers the most...
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