Responsibilities include but not limited to the following:
• Provide expertise for test solutions during design planning/budgeting/implementing.
• MBIST new feature implementation and validation: BIST architecture planning, memory grouping, pattern generation and validation, silicon bring-up, diagnostics analysis and debug.
• Scan implementation at core, subsystem & SoC level
• MBIST & Scan simulation experience – notiming & SDF simulations
• Participation in customer’s design and flow reviews.
• Drive, Prototype & Develop new Design for Test methodologies.
• Ability to multitask across many issues and priorities, and the desire to help customers exploit new technologies are essential for success in the position.
Qualification
• BS+5 years of relevant experience/MS+3 years of relevant experience in Electrical Engineering or Computer Engineering or other relevant field of study.
• Experience in handling Memory BIST & Scan for couple of designs atleast
• Experience with RTL Coding, Scan/ATPG/MBIST - Insertion, Validation, Pattern generation & silicon bring-up
• Exposure to Memory architecture, fault models, MBIST algorithms, hard/soft repair and efuse repair flow
• Good understanding of protocols like 1149.1, 1500, 1687
• Good soft skills
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