Verification Leader

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.


Senior Staff Digital Design Verification Engineer


In this role you will be focusing on functional and timing verification of digital and mixed-signal designs.  The verification tasks may include both block-level and chip-level designs. The successful candidate will work on a variety of verification tasks including generating verification plans, testbench / testcase development, automating / reporting / maintaining various forms of coverage metrics, and reviewing / auditing work of other verification engineers. This position may also be involved with the customer support team including direct interaction with customers as needed in relation to both pre-sales and post-sales support. As a Senior Engineer, the individual in this role is expected to plan verification tasks for multiple projects, assist with the guiding of tasks, and oversee the work of other verification engineers. 
 
The responsibilities of this role include, but are not limited to: understanding and possibly assisting in the generation of design specifications; developing and executing functional test/verification plans; developing verification environments and testing suites for chip and block level testing using the latest tools and verification languages; writing behavioral models; this role may also perform mixed-mode (digital + analog) simulations.
 

• BSEE degree or Applied Science degree (or equivalent) with 15+ years of related experience as well as experience in verifying designs at the chip level and block level.
• You have been leading and driving large and small verification projects with hands-on experience leading the efforts of anywhere from 2-10+ engineers as the technical prime.
• Strong Verilog and SystemVerilog and deep knowledge of the UVM methodology are a must.
• Candidates will have knowledge of System Verilog Assertions and/or assertion based verification.  Knowledge of IP development and/or the DDR memory protocol are valuable assets as are scripting languages such as Python, PERL and TCL.
• Candidates will have experience with back-annotated gate level simulations at the chip level and block level.
• Excellent communication and presentation skills.
• Well organized, methodical, detail oriented and possess knowledge in product debugging.
• Previous knowledge in customer support is an asset.