Staff Logic Design Engineer

Staff Logic Design Engineer

Synopsys Inc. is looking for a full-time candidate to work on the industry's leading and fastest emulation and prototyping system, HAPS, which offers the industry's largest design capacity, based on high-density 7 nano-meter FPGA technology. In HAPS emulation/prototyping flow, the design under test is partitioned into multiple parts, each of which is compiled into a low-level binary bit-stream that can be downloaded and run on an underlying FPGA in the emulation/prototyping hardware.

Individuals that fill the position will work in a global multi-site team specializing in areas such as logic implementation, verification, partitioning, static timing analysis, and timing performance optimization to design and develop the next generation emulation/prototyping verification technologies used in HAPS tools. The responsibilities include innovating good ideas to solve challenging practical problems, developing digital logic based on the selected innovative idea, and demonstrating the correctness and effectiveness of it by running benchmarking designs and comparing the results.

Description:

• Responsible to interpret requirements and to define, design, develop, maintain and improve firmware in FPGA based emulator/prototyping system.
• Develops RTL code for the FPGA system, implements functional blocks from scratch or utilizes in-house or third-party IPs, and verifies them in a timely manner.

Requirements:

• BS/MS/PhD in Electrical, Electronic, Computer Engineering or Science, or related areas
• Proficient in Verilog, Verilog 2001 or System Verilog
• Independent problem-solving skills and team work skills

Experience in the following areas is highly desired:

• Block to module level architecture/spec definition
• Embedded processor RTL implementation
• High bandwidth/low latency/pipelined data channel, and switches RTL implementation
• Host interface and DMA processor RTL implementation
• IP usage, such as PCI Express controller, DDR3/4 controller, Multi Gigabit Transceiver, SerDes
• FPGA resource utilization, placement, routing, and timing optimization
• TCL/C/C++/Python/Perl

ABOUT US
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.

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Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

The base salary range across the U.S. for this role is between $111,000-$167,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.

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