ASIC Digital Design Engr, II

The selected candidate will be part of the DesignWare IP R&D team at Synopsys. The candidate will be expected to specify, design/architect and implement Verification environments for the synthesizable DesignWare cores and perform Verification. Candidate will work closely with RTL designers, Architects and be part of a global team of experienced Verification Engineers. Job role demands Test planning, Testbench coding both at unit level and system level. Testcases/Coverage coding, reviews, regressions management and meeting quality metric goals. The candidate will be part of the Solutions Group, India. This is a Technical IC role and offers challenges to work in a multi-site environment with good. The position offers to work on NextGen DesignWare IPs and with good learning and growth opportunities.

Key Qualification:

• BS/MS in EE/EC/VLSI stream with 4+ years of relevant experience in the verification of IP cores and/or SOC.
• Must have proven experience in developing HVL (System Verilog/UVM) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage and Code coverage.
• Experience on memory interface protocols (DDR, LPDDR) is highly desirable.
• Exposure to IP design and verification processes including VIP development is an added advantage.
• Good communication skills, debug and problem-solving skills and should be self-motivated.

Preferred Experience:

• Be a technical contributor in the Verification Tasks – System Verilog/Verilog coding of testbenches, Test cases, performing verification tasks such as coverage, debug, regressions using the latest methodologies such as UVM, Formal verification etc.
• Creates deliverables which do not require close review or supervision by a Senior Technical Engineer.
• Be able to study the coverage metrics and improve them with definition of additional test cases in directed environment, at least for small/ medium complexity features of the protocol/ product specs.
• Familiarity with HDLs such as Verilog and scripting languages such as shell/Perl/Python etc. is highly desirable.
• Works in a project and team-oriented environment with teams spread across multiple sites, worldwide.

Soft Skills:

• Good team player with interpersonal and communication skills.
• High levels of motivation and self-propulsion.

Business Area Description:
Our Silicon DV business is all about building high performance silicon chips faster. We're the world's leading provider of solutions for designing and verifying advanced Silicon chips. We design the NextGen processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost and performance.

About Synopsys:
At Synopsys, we're at the heart of the Innovations that change the way we work and play. Our chips are everywhere (Self driving Cars, AI, HPCs, 5G, IOT, etc.) enabling the Era of Smart Everything. We're powering it all with the world's most advanced technologies for chip design and SW security.

EEO:
Inclusion & Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status or disability.