Analog design, Senior engineer

Qualifications:
Key Qualifications:
·         Btech/Mtech with 2-10 years of SerDes/High-Speed analog design experience.

Experience in design of Analog front-end transceivers, voltage/current-mode drivers , PLLs, Regulators, Bandgaps, Equalizers (CTLE, FFE, DFE), Impedance calibrators, serializer , De-serializers , voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference,  etc.

Hands ON experience with spice simulations and various sub-micron design methodologies. Familiarity with automation / Scripting language(TCL, PERL).

Silicon-proven experience implementing circuits for analog and mixed-signal building blocks. Can micro architect circuit from specifications, can create simulation benches to verify the specification, can understand and debug circuit.

Experience optimizing CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.

Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.).

JOB Responsibilities
·        Ensure analog sub-block performance adheres to SerDes standards and architecture document specifications.
·        Identify and refine circuit implementations to achieve optimal power, area and performance targets.
·        Propose design and verification strategies that use simulator features to ensure highest quality design.
·        Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
·        Collaborate with digital RTL engineers on the verification of calibration, adaptation and control algorithms for analog circuits.
·        Present simulation data for peer and customer review.
·        Ownership of analog and mixed-signal building block that is integrated as part of a larger SerDes design.
·        Document design features and test plans.
·        Consult on the electrical characterization of your circuit within the SerDes IP product.


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