ASIC Digital Design Engineer, Staff Engineer

Job Description: 
The selected candidate will be a technical leader of the Synopsys DesignWare Processor team in Hsinchu involving in development of leading edge DesignWare processor IP products such as HPC processors, NN accelerators, vision processors, as well as energy-efficient processors. 
The responsibility is to take full ownership and accountability on quality of delivery for at least a block of design f and/or verification functions within a product development effort. This may include but not limited to authorship of plans and specs for owned functions, guiding, coaching, and tracking others for appropriate execution with necessary technical works, as well as escalation of overall team competences. The technical works could be applied to architecture, micro-architecture, logic design, verification and validation, as well as related engineering flows or environments and necessary signoff delivery processes. Depending on individual’s capability and career development, the works may include but not limited to investigation, creation, implementation, analysis, debugging, and optimization in said areas. In addition, the candidate would have great opportunities to collaborate with cross-team or cross-site colleagues on various technical matters such as algorithms, methodologies, quality of delivery, SoC prototyping, system bring-up, or any other engineering works that are required for overall business operations. 
  
Job Requirements: 

• Master degree in EE or CS related engineering major is required as a minimum from a reputed college 
• Minimum 4 to 9 years of experience in digital frontend design or verification 
• Comprehensive knowledge in microprocessor architecture, memory subsystem architecture, and computer system architecture 
• In-depth hands-on experiences in architecture and micro-architecture definition, RTL design, RTL and model co-simulation, regressions, and respective debugging activities 
• HDL and Verification languages: SystemVerilog, Verilog 
• Micro-architecture and RTL design, or verification methodologies such as UVM/OVM, functional formal, functional coverage 
• Other Programming skills: C/C++, Python, scripts, or assembly, 
• Tools: RTL linters, simulators, functional formal, functional coverage, team work tools (continuous integration, source control management, issue tracking, etc.), ADL-based generation tools (such as Synopsys ASIP Designer) 
• Experience with multi-site development is helpful 
• Written and Verbal communication skills: 
  • Creation, modification and review of documentation: design or verification work plans, engineering quality processes, test scenarios, test reports 
  • Ability to profile the values, requirements, issues, risks, and solutions for engineering works presentation for leadership review 
  • Ability to follow disciplines describing issues and changes in track systems 
• Analytical skills: 
  • Analysis of signoff requirements for product releases 
  • Ability to analyze and track design or verification results, quality and risk, for major milestone reviews and assessments 
• Self-motivated team player who is able to thrive in a fast-paced engineering environment 
• Ability to motivate and influence team member toward desired results