Std Cell Library Applications Engineering, Sr Staff Engineer

We are looking for motivated Applications Engineer to develop and support library modeling solution for advanced process nodes, enabling Synopsys Digital Design Family customer success.

The primary focus of the Applications Engineer is to help our customers with the adoption and continuous usage of Library Compiler and optimized library modeling solution to enable chip designers achieving best Power/Performance/Area Goals using Synopsys Digital Design Family.  Synopsys’ Library Compiler tool is the industry leading library solution that addresses existing and emerging logical, electrical, and physical modeling challenges in advanced process node.

The engineer will closely work with Library Compiler R&D team, and AEs in Synopsys Digital Design Family of products, to influence technologies/solution roadmaps and provide R&D team with accurate input from field, helping them focus on the most critical design challenges.
The engineer will work with other Synopsys AEs, ensuring overall consistency of end-to-end design flow and meet customer needs.


Main responsibilities:

· Engineer will use in-depth product knowledge to provide technical expertise to customer to help solve day to day technical problems and help develop industry leading library modeling solution.
· Provide consultation to prospective users and/or product capability assessment and validation.
· Provide tool trainings.
· Provides technical expertise to sales staff through sales presentations and product demonstrations.
· Assists the sales staff in assessing potential application of company products to meet customer needs and preparing detailed product specifications for the development and implementation of customer applications/solutions.

Requirements:

We are looking for an innovative, motivated and dependable person, with at least BSc degree and 10 years of recent hands-on experience including:
· Solid knowledge of digital design flow concepts and engineering fundamentals.
· Solid knowledge in transistor-level design to debug circuit level issues.
· Good knowledge of TCL and other UNIX scripting languages. (Python is a plus.)
· Very good English communication and social skills.
· Has a desire to learn and explore new technologies or tools.

Plus:

· Static Timing Analysis, logic synthesis, and/or automatic place and route experience.
· Library Compiler and Liberty modeling language experience highly desirable.
· Experience in advanced technology nodes preferred.