Digital Design Verification Staff Engineer

The Digital Design Verification Staff Engineer works on PHY IP verification related to complex protocols. The position offers excellent learning and growth opportunities. This is a technical individual contributor role offering a challenging career path.

The role involves developing and working on verification of high speed PHYs and Serdes. Additionally, you will be involved in:

• Verification plan development and its review
• Verification environment development
• Debug of simulations, including those of real signals modeled using SV for analog.
• RTL, GLS, Co-simulations, FW simulation & coverage closure
• Deliver high quality RTL and other simulation models to customer.
• Participate in technical reviews and contribute actively.
• Participate in customer support with bring-up of IP in customer simulation environment.
• Participate in review of SERDES / PHY / Controller IP specification to validate compliance to protocol of interest.
• Follow and improve development process ensuring high quality output.

Skill Set:
B.Tech/M.Tech with 5+ years of relevant experience. 
Hands on experience in creating detailed Verification Environment from Functional Specifications
Knowledge of protocols like 25G/50G/100G Ethernet, PON, other networking protocols
Test planning, Coverage and Assertion planning.
Hands on experience with System Verilog, mythologies like VMM/UVM, simulation and debug tools.
Experience with Version Control tools like Perforce/SVN.
Knowledge of Perl/Shell scripts
In addition, the candidate should have good communication skills, be a team player with good problem solving and interpersonal skills.

Inclusion and Diversity are important to us at Synopsys. Synopsys considers all applicant for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status or disability.