Junior Verification Engineer

Our Digital Team is seeking for great Design Verification engineer. Join with us if you are finding a job which challenge yourself with latest process technologies.

Opportunities:

• SNPS is the world number one IP provider. To be trained and developed by many experts from around the world and talented Vietnam engineering team.
• Professional, innovative, fair and fun working environment.
• Competitive salary and benefit such as health Insurance, Football, Table tennis, Badminton, Yoga, Zumba Clubs.
• Team building activity: Team trip, Family Day…
• Opportunity to work with the complete design flow for a complicated Analog Mixed Signal Design from specification to silicon.
• Clear career path of self-development to either Technical Experts or Manager
• Travel to USA, Europe and Asia for training or on-site support.

Job Descriptions:

• Work in the RnD team to develop and validate for the high-bandwidth interface IP.
• Hands on experience in creating detailed Verification Environment from Functional Specifications
• Writing test cases, checkers, and doing coverage report.
• Debug of simulations, including those of real signals modeled using SV for analog.
• RTL, GLS & Co-simulations & coverage closure
• Take part in technical reviews, peer review.
• Follow and improve development process ensuring high quality output.

Skills Requirements:

• BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.
• 2+ years of experience in Design Verification
• Experience in skill with design tools: VCS, Verdi. Familiar Formal verification tool (vc_formal) is a plus.
• Excellent debug skills and demonstrated experiences in Perl /TCL/Python scripting is a plus.
• Accountable, result oriented and good English communication.
• Great team player, willing to support others.
• Self-motivated and enthusiasm in technology and problem solving.