Analog Layout Design, Senior Staff

Opportunities

• SNPS is the world number one IP provider. Work with many experts from around the world and talented highly motivated Vietnam engineering team. 
• Have opportunity to have experience with the best set of tools in the industry to support for your design tasks. 
• Professional, innovative, fair and fun working environment. Strong culture company.
• Competitive salary and benefit. Strong support from company for health: Insurance, Sport clubs: Football, Ping-Pong, Badminton, Yoga, Zumba …
• Strong support from company for team building, social activities: Team trip, Family Day…
• Opportunity to get in touch with the complete design flow of a real complicated Analog Mixed Signal Design from specification to silicon.
• Chance to work with bleeding edge technologies like: 2.5D/3D IC, High-speed Die to Die interfaces that enable Data Center, AI/ML, 5G applications.
• Clear career path of self-development to either Technical Expert or Design Leader/Manager
• Travel to USA, Europe, and Asia for training or on-site support.
• Showcase your brilliant ideas in conferences that sponsored by Synopsys
• Contribute to the growth of Vietnam semiconductor industry with many big programs of Synopsys for universities and design community. 

 
Job Descriptions
 

• Design circuit for Analog IPs like High Speed IOs, PLL, DLL, Bandgap,  Clock trees, Calibration circuits... for Die to Die, UCIe, DDR, HBM, Serdes PHY of Synopsys.
• Work closely with layout engineer to make sure layout quality. Perform post layout verifications.
• Design analysis  and solve problems of noise, margin, signal integrity, power integrity.
• Complete all design quality checks and data quality checks
• Do design reviews across global team
• Work with digital/system engineer to integrate analog designs into mixed signal system. Perform mixed signal verification which combining both analog and digital blocks.
• Design test chip architecture to test analog designs.
• Build up test cases and run tests in the Synopsys Laboratory to prove design work in silicon.
• May join research programs to implement new ideas for future products and flows.
• May lead a team to develop a completed design.
• Training for junior engineers and interns

 
Skills Requirements

• BS in Electronics Engineering, Electromechanics, Physics, Telecommunications.
• At least 10 years of experience in custom layout.
• Familiar with Layout entry tools: Cadence, Synopsys
• Familiar with Layout verification tools: Mentor Calibre, Synopsys ICV
• Understand basic semiconductor fabrication processes
• Understand MOSFET fundamentals
• Understand layout techniques for high speed, matching, ESD, Latchup, Antenna, EMIR.
• Experienced with mentoring/leading junior layouts to complete a design.
• Experienced with writing layout review presentations and layout verification reports
• Good English communication
• Strong team player
• Self-motivated, humble, honest and willing to learn.

Synopsys delivers the most trusted and comprehensive silicon to systems design solutions, accelerating technology innovation. We partner closely with our customers to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. Companies trust Synopsys to pioneer new technologies to help them get to market faster without compromise.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.