ASIC Digital Design Engineer, Staff

ASIC Digital Design Engineer, Staff


The candidate will be part of the R&D in Solutions Group at our Bangalore Design Center, India. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in a role that will include IP RTL Design and Design verification using latest design verification methodology Flows.

Job Description
The candidate will be part of the DesignWare IP Design R&D team at Synopsys. He/She will be expected to specify, design/architect and implement state-of-the-art RTL for the DesignWare family of synthesizable cores and perform Design Verification tasks for the IP cores. He/She will work closely with RTL verification team and be part of a global team of expert Design Engineers. He/She will also work closely with other IP design teams and IP support teams.
Will be working on the next generation connectivity protocols for Commercial, Enterprise and Automotive applications
Job role will have a responsibility of Functional specification development, Micro architecture development, RTL development and unit level testing, RTL reviews, exercising the RTL with various design flows, debugging and supporting the verification team on meeting the coverage Metrix.

Requirements:
Must have BSEE in EE with 4 to 8+ years of relevant experience or MSEE with 3 to 7+ years of relevant experience in the following areas:
- Must have experience in developing Functional specification, Architecture, micro architecture and HDL (Verilog) based implementation.
- Must have strong HDL coding skills for RTL development, must have expertise in developing the RTL code which is multi-clock domain, complex FSM, Frame structure implementation, Data path and control path implementation.
- Expertise in design tool flows such as Spyglass, VC-Spyglass, STA, DC, Fusion Compiler, Formality, Prime Time is must.
- Knowledge of one or more of protocols: MIPI-I3C/UFS/Unipro, AMBA (AMBA2, AXI), SD/eMMC,  Ethernet,  DDR, PCIe, USB
- Familiarity with HVLs such as System Verilog  and scripting languages such as Perl, TCL, Python is highly desired.
- Exposure to IP design and design processes is an added advantage.
- There will be strong focus on functional coverage driven methodology. So, the corresponding mindset is a must.
- It is essential that the individual has good written and oral communication skills and can demonstrate good analysis, debug and problem-solving skills and show high levels of initiative.

This position requires prior industry experience and is not open for college fresh grads.

Location:  Bengaluru
 
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.