ASIC Digital DV, Staff Engineer

Job Description And Requirements 
 
INDIA - Bangalore 
 
Designation: ASIC Digital Design , Staff Engineer 
 
The candidate will be part of the R&D in Solutions Group at our Bangalore Design Center, India. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in a role that will include IP Design Verification using UVM based environment methodology. 
 
Job Description: The candidate will be part of the Synopsys IP Design verification R&D team at Synopsys. You will own UVM based verification environment, which handles multiple features of IP, test plan creation, test case writing, random constraint creation, coverage closure, SVA and Release As part of the work, you will closely work with lead and be part of a global team of experienced Engineers. 
 
Technical Expertise Needed : 
 

• Must have BSEE in EE with 4+ years of relevant experience or MSEE with 3+ years of relevant experience in the following areas: 

• Own UVM based testbench environment and developed UVM testbench architecture, Testplan and SVA for an IP/SoC. 

• Knowledge of one or more of protocols/standards: VESA VDC-M, DSC, HDMI 2.1, MIPI DSI, AMBA (AXI,APB,AHB) 

• Good knowledge of Verilog/System Verilog/C/C++. 

• Hands-on experience in writing script on shell, csh, TCL and python.   

• Hands-on experience with coverage closure and writing SVA for IP/SOC. 

• Good debugging skills. 

• Experience with Perforce or similar revision control environment. 

• Exposure to quality processes in the context of IP verification is an added advantage 

• Job Responsibilities include - 
   

• Understand Standard Specifications, create testplan for the product and create UVM based testbench architecture. Propose and enhance the UVM architecture with unique idea for verification. 
   

• Be single point of contact with hands-on experience on all verification tasks – Testbench Creation – Testplan creation – Coverage closure – SVA – Release 

• Perform peer review of testbench code for continuous quality.  

• Own simulation debugs using DVE/Verdi, interact with Design Team and aid in debug and Verification closure  

• Periodically publish technical papers and/or file patents on the feature updates/innovation carried out 
   

• The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide 

• In addition, the candidate should have excellent oratory and written communication skills in English, should be a team player and possess good problem-solving skills and show high levels of initiative. 

This position requires prior industry experience and is not open for college fresh grads. 
 
Location: Bangalore 

• Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.