As a Front-end SOC engineer, you will be responsible for co-working with BE engineer or customer's engineers to assist our customers tape out successfully from RTL to GDS or from Netlist to GDS by using Synopsys EDA tools. Your main focus will be in the areas of physical synthesis, design/constraint QA, DFT/ATPG tasks, formal verification, VCLP, STA and timing ECO. You will be working as a member of the customer's IC design team, leveraging your experience and Synopsys' best practices to have immediate impact on their current project while transferring valuable knowledge for future projects. Interacts regularly with customers to identify and eliminate barriers to project success. Plans and manages delivery of own project-related tasks. Leverages entire Synopsys team to ensure project success. Provides feedback to R&D/AE on suggested tool enhancements or issues. Works with or as Project Leader to develop technical proposals, working through project life cycle and produces consistently high quality technical solutions.

Typically requires BSEE or higher with 12+ years industry experience. • Familiar with physical synthesis. • Familiar with STA. • Good at design/constraint QA by SpyGlass. • Formal Verification and DFT/ATPG. • Familiar with UPF and low power related knowledge is better. • Experience of some physical implementation is better. • Knowledge/experience of design coding is better. • Demonstrate solid verbal and written English communication skills, and customer interfacing skills. • Demonstrate the ability to work in a stressful environment with a broad array of individuals in a cross-functional team. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

 

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