Main Responsibilities.
  • Working on subblock level to top level SERDES designs such as RX_CDR, DDL/DLL, RX_EQ, TX_SER and RX_DES blocks, true expert for TX/RX top architectures. Simulating, analyzing, debugging issues.
  • Can easily read databook and specification books for MIPI DPHY/CDPHY product line. Updates existing specs according to latest requirements. Do verifications on new ported design blocks, find week point, debug and provide sch and architectural solutions.
  • Be able to work with different sites, supervise juniors and actively sharing knowledge/experience through owning design flows and special training to others.

Preferred Experience

  • Review SerDes standards to develop analog sub-block specifications
  • Identify and refine circuit architectures to achieve optimal power, area and performance targets
  • Propose design and verification strategies that efficiently use simulator features to ensure highest quality design
  • Oversee physical layout to minimize the effect of parasitics, device stress, and process variation
  • Present simulation data for peer and customer review
  • Document design features and test plans
  • Consult on the electrical characterization of your circuit within the SerDes IP product

 Key Qualifications:

  • PhD with 3 year, or MSc with 7 years of analog IC design experience
  • In depth familiarity with transistor level circuit design - sound CMOS design fundamentals
  • Detailed design experience with at least one, and familiarity with several other SerDes sub-circuits: receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializes, voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, DAC
  • Aware of ESD issues (i.e. circuit techniques, layout)
  • Familiarity with custom digital design (i.e. high-speed logic paths)
  • Knowledge of design for reliability (i.e. EM, IR, aging)
  • Knowledge of layout effects (i.e. matching, reliability, proximity effects)
  • Experience with tools for schematic entry, physical layout, and design verification
  • Hands-on experience with physical layout of high-speed circuits is a plus
  • Knowledge of SPICE simulators and simulation methods
  • Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture
  • Experience with TCL, Perl, C, Python, MATLAB, or other scripting languages is desired
  • Good communication and documentation skills
Is a Remote Job?
No

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