3DIC/CoWoS Design and Flow Development leader

At Synopsys, we’re at the heart of the innovations that change the way we work and play.  Self-driving cars. 3DIC. Artificial Intelligence. Machine learning. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Job Description: 
This job is for a 3DIC Design Methodology and Flow Development leader in Synopsys' System Solution Group (SSG) team. The candidate should have experience in 3DIC design flow integration and be responsible for developing the design methodology/flow, working with cross-functional teams and customers, and identifying potential flow issues. The candidate should also have expertise in areas such as design partition, floor planning, I/O and Bump/TSV planning, design flow integration, and thermal analysis using commercial EDA tools. The ideal candidate should be self-motivated, detail-oriented, and have strong coordination and partnership skills.
 
Qualifications: 
n   The minimum qualifications for this position include a MS/Ph.D. degree in Electrical Engineering, Computer Science, or a related field of study
n   With 5+ years of experience in 3DIC and CoWoS (Si interposer) design, flow development, or EDA enablement.
n   Floor planning and AP/metal routing
n   It would also be helpful if the candidate has a good relationship with couple of larger foundries.
n   The candidate requires a minimum of 3+ years' experience in ASIC (APR) design, knowledge at least one of the following areas: Analog or Digital IC design, semiconductor manufacturing, assembly, and packaging basics
n   A technical background in EDA tools as the user.
n   The candidate should also have programming skills in one or more of the following: TCL, SKILL, Python.
n   In addition to the mentioned qualifications, candidates with a demonstrated ability to devise innovative design solutions will be highly valued.
 
Preferred qualifications:
n   Experience with 2/2.5D and/or 3D integration chip design projects
n   Experience in 2/2.5D and 3D simulation tools and methodology, particularly for signal integrity and power integrity.
n   Experience in ASIC/SOC (APR) FE/BE design methodology/flow is a plus.
n    Working directly with Foundries and understands the IC manufacturing and has taken several design through tape-out and Foundry sign-off process.
n   The ideal candidate should have evidence of strong organizational and planning skills for engineering projects and possess good communication and presentation skills for executive project coordination.
n   The candidate should also have experience working with multiple function teams for EDA tool collaboration.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.