ASIC Digital Design Engr II

The candidate will be part of the DesignWare IP Design R&D team at Synopsys. He/She will be expected to specify, design/architect and implement state-of-the-art RTL for the DesignWare family of synthesizable cores and perform Design Verification tasks for the IP cores. He/She will work closely with RTL verification and be part of a global team of expert Design Engineers. He/She will also work closely with other IP design team and IP support team.
Will be working on the next generation connectivity protocols for Commercial, Enterprise and Automotive applications
Job role will have a responsibility of Functional specification development, Micro architecture development, RTL development and unit level testing, RTL reviews, exercising the RTL with various design flows, debugging and supporting the verification team on meeting the coverage Metrix.