ASIC Digital Design Engr, Sr II

Job Responsibilities

• Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design documents for some of the components of the design with medium complexity.
• Be an individual contributor in the Design Tasks – RTL coding of design, debug, verification coverage improvement in the directed Verilog Test Bench, etc.
• Create/ work on designs using Low Power Design Methodology and automotive safety.
• Need to understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design documents for some of the component's functions/ product features for the DesignWare family of synthesizable cores in protocol areas such as VESA-DSC/AMBA (AMBA2, AXI, CHI)/ SD/eMMC/DDR/PCIe/Ethernet/ USB/ MIPI
• Creates deliverables which do not require close review or supervision by a Senior Technical Lead.
• Do technical review of Functional specification, micro-architecture and RTL Code.
• The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in directed environment, for features of the protocol/ product specs.
• The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide.

Key Qualifications and Experience
Must have BSEE in EE with 5+ years of relevant experience or MSEE with 4+ years of relevant experience in the following areas:

• Design of IP Cores or SoC Designs.
• Knowledge of one or more of protocols: VESA-DSC, AMBA (AMBA2, AXI, CHI)/ SD/eMMC/DDR/PCIe/Ethernet/ USB/ MIPI. Knowledge of Ethernet protocol is highly preferred.
• Hands on experience with creating micro-architecture/ detailed design from Functional Specifications for small/ medium design complexity. Must have worked on control path-oriented designs like asynchronous FIFO, DMA architectures, SPRAM/ DPRAM interface design, etc.
• Understanding and prior experience of data-path designs and implementation of arithmetic algorithms such as for FEC etc. will be plus.
• Hands on experience with Verilog/ System Verilog coding and Simulation tools
• Synthesis flow and static timing flows, Lint, CDC, Formal checking, etc. is a must for candidates with design background.
• Experience with Perforce or similar revision control environment.
• Knowledge of Perl/Shell scripts.
• In addition, the candidate should have good communication skills, should be a team player and possess good problem-solving skills.