ASIC Digital Design Manager

The selected candidate will be part of the DesignWare IP R&D team at Synopsys. the opening is for a Verification manager. The candidate will be expected to specify, design/architect and implement Verification environments for the synthesizable DesignWare cores and perform Verification. Candidate will need to lead a team of around 5 to 10 verification engineers and guide the team towards closure of day to day verification activities like test and TB component development, regression debug triaging, and make sure product release based verification milestone are met, Candidate will work closely with RTL designers, Architects and be part of a global team of experienced Verification Engineers. Job role demands, Understand the Design specifications, Think about the usage scenarios, Test planning, Testbench coding both at unit level and system level. Testcases/Coverage coding, reviews, regressions management and meeting quality metric goals. The candidate will be part of the Solutions Group, India. This is a Technical Manager role and offers challenges to work in a multi-site environment with good exposure to different people and skillset development. The position offers to work on NextGen DesignWare IPs and with good learning and growth opportunities.

Key Qualification:

• BS/MS in EE/EC/VLSI stream with 10-15 years of relevant experience in the verification of IP cores and/or SOC
• Experience in leading a team of engineers.
• Hands on experience on verification of complex designs at IP or/and SoC level.
• Strong knowledge of Verilog/System Verilog language is needed.
• Strong and deep experience in Testbench development and UVM environment is needed.
• Experience in memory protocols like DDR/LPDDR5 is desirable.
• Exposure to IP design and verification processes including VIP development is desirable.
• Exposure to Perl/Python based automation is desirable.
• Good communication skills, debug, and problem solving skills, and should be self motivated

Preferred Experience:

• Be a strong team leader, motivator with a go-getter attitude.
• Be a technical contributor in the Verification Tasks – System Verilog/Verilog coding of testbenches, Test cases, performing verification tasks such as coverage, debug, regressions using the latest methodologies such as UVM, Formal verification etc.
• Creates deliverables which do not require close review or supervision by the senior management.
• Understand needs of verification milestones and align the team tasks accordingly. 
• Be able to study the coverage metrics and improve them with definition of additional test cases in directed environment, at least for small/ medium complexity features of the protocol/ product specs
• Familiarity with HDLs such as Verilog and scripting languages such as shell/Perl/Python etc. is highly desirable
• Works in a project and team oriented environment with teams spread across multiple sites, worldwide.

Soft Skills:

• Good team player with inter personal and communication skills.
• High levels of motivation and self-propulsion.

Business Area Description:
Our Silicon DV business is all about building high performance silicon chips faster. We're the world's leading provider of solutions for designing and verifying advanced Silicon chips. We design the NextGen processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost and performance.

About Synopsys:
At Synopsys, we're at the hear of the Innovations that change the way we work and play. Our chips are everywhere (Self driving Cars, AI, HPCs, 5G, IOT, etc.) enabling the Era of Smart Everything. We're powering it all with the world's most advanced technologies for chip design and SW security.

EEO:
Inclusion & Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status or disability.