Staff Analog Design Engineer

Synopsys is looking for Senior Analog Design Engineer to work on next generation of PLLs for world leading system-on-chip (SOCs) in leading edge CMOS technology nodes!
This position targets Engineers for the design, verification and validation of integrated, high-performance, high-speed analog circuits.
The focus of the work will be on design of Phase Lock Loops, Delay Locked Loops, Phase mixers and custom digital blocks used in SERDES interfaces.
The candidate will work on a variety of tasks, incorporating such tasks as, and not limited to, test bench and specification generation, analog circuit design and layout optimization, documentation, design debug and silicon evaluation.

Key Qualifications:

• University degree in Electronics/Engineering
• Good understanding CMOS technologies.
• Good working experience in analog and mixed-signal block design, preferably related to high speed SERDES (Drivers, Receivers, Clocking, PLL, DLL, CDR).
• Familiarity with UNIX operating systems.
• Ability to build relations and keep teamworking.
• Good written and verbal communication skills in English and Polish and problem-solving skills.
• Organizational skills are essential.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.