ASIC Digital Design Engr, Sr II

Job Overview

Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. Synopsys DesignWare SERDES PHY is uniquely positioned in the industry as one of the most complex and high performing IP, in terms of interface, feature support as well as deployment across a wide spectrum of customer products. We are looking for a full time IP RTL Design position to work on our High Speed SERDES PHY development.

Location: Hyderabad

Preferred Qualifications
 

• Bachelor's or Master’s degree in relevant field
• 8 to 12 years of relevant experience in micro-architecture, digital design and RTL coding.
• Must have strong Digital Design fundamentals
• Extensive practical hands-on experience in defining micro-architecture and RTL Coding for IP blocks
• Working knowledge and experience on high-speed interface protocols (PCIe/Ethernet) is highly desirable.
• Knowledge in Verilog/VHDL coding, Spyglass LINT/CDC/RDC checks and waiver creation.
• Knowledge in Synthesis, STA, Formal checking, etc.
• Knowledge in Verification and debugging issues.
• Understanding of RTL to GDS flow.
• Familiarity with scripting languages such as Shell/Perl etc. is highly desirable. 
   

Key Responsibilities

• Understanding IP Specifications
• Defines and develop micro-architecture
• RTL Design using Verilog/System Verilog
• Interacting with cross functional teams to resolve the issues in creative way
• Helping verification team to debug the issue
• Running ASIC development tools including Lint and CDC
• Guides junior peers with aspects of their job