MIPI ASIC Digital Verification Engineer, Senior

The candidate will be part of the R&D in Solutions Group at our Bangalore/Pune Design Centre, India. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers opportunity to work in a multi-site environment  on IP verification of complex cores using latest verification methodology.
Job Description
The candidate will be part of the DesignWare IP Verification R&D team at Synopsys. He /She will be expected to specify, design/architect and implement state-of-the-art Verification environments for DesignWare family of synthesizable IP cores and perform Verification tasks for the IP cores. He/ She will work closely with RTL designers and be part of a global team of expert verification engineers.
Will be working on the next generation connectivity protocols for Commercial, Enterprise and Automotive applications
Job role will have a combination of test planning, test environment coding both at unit level and level, creation of test scenarios, debugging, FC coding /analysis, meeting quality metric goals and regression management.
 
Requirements:
Must have BSEE in EE with 8+ years of relevant experience or MSEE with 7+ years of relevant experience in the following areas:
- Must have experience in developing HVL (System Verilog) based test environments, developing, and implementing test plans, implementing, and extracting verification metrics such as functional coverage.
- Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform based debugging tools.
- Exposure to verification methodologies such as VMM/OVM/UVM/ is required.
- Knowledge of one or more of protocols: MIPI-I3C/UFS/Unipro, AMBA (AMBA2, AXI) is highly desirable, exposure to others protocols such as SD/eMMC,  Ethernet,  DDR, PCIe, USB is a plus
- Experience with verification of  Scatter Gather DMA. Host controller interface is a significant plus.
- Experience with HDLs such as Verilog  is a must and scripting languages such as Perl, TCL, Python is highly desired.
- Exposure to IP design and verification processes including VIP development or Formal verification is an added advantage.
- There will be strong focus on functional coverage driven methodology.
- It is essential that the individual has good written and oral communication skills. The candidate shall demonstrate good analysis, debug and problem solving skills and show high levels of initiative.
 
This position requires prior industry experience and  is not open for college fresh grads.
 
Location:  Bengaluru/Pune
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.