ASIC Digital Design Engineer, Staff

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

We’re looking for ASIC Digital Design Engineer, Staff for the High Bandwidth Memory PHY RTL team

In this role you will be joining an experienced RTL team developing in leading-edge technology. The group is designing High Bandwidth Memory PHY IP at the boundary of digital, mixed signal and analog. With your understanding of highspeed circuit design you will deliver RTL and technical support to a variety of teams.

Synopsys has offices all over the world and you will have the opportunity to work with people across many sites and time zones. You will be working from an Architecture and Industry Standard Specifications to develop, deliver and support RTL designs in leading-edge technologies.

Key Qualifications

• A history of excellent problem-solving skills
• Clear communication both written and oral
• Highspeed design and timing closure
• Designing RTL with SystemVerilog and Verilog
• Capable of automating repetitive tasks using a variety of scripting languages
• 5-10 years of experience in RTL design, including interfacing with Mixed Signal Designs
• Interfacing with Analog and Mixed Signal designs
• Writing clear specification documents
• Experience of entire ASIC and IP development flow
• Aware of DFT/DFM flows
• Experience of debugging complex hardware issues
• Interfacing with Mixed Signal Designs
• Capable of modeling Analog and Mixed Signal Circuits

Preferred Experience

• Capable of setting up and debugging physically aware synthesis
• DDR and HBM DRAM technologies

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact [email protected].
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