Synopsys' high-speed interface IP (PCIE/CXL/USB/DP) subsystem solution is gradually becoming a key module of AI acceleration, GPGPU, Big-Data SOC chips. More and more customers have adopted Synopsys' latest PCIE GEN6 with CXL/IDE to increase product bandwidth, improve security, reduce system latency, and meet the high bandwidth demands of high-end SOCs such as various cloud services, AI, and GPGPU. If you are interested in joining us and contributing to the rapid development of the industry, maybe you are the one we are looking for.
We’re looking for an IP (PCIE/CXL/USB/DP) Subsystem Design or Implementation or Verification Engineer to join the team. This role involves developing and verifying integrated Interface IP Subsystems. Additionally, you could create design and verification specifications.
Key qualifications:
- Bachelor’s or master’s degree.
- Minimum 3 years of IP or ASIC Design/Verification/Implementation experience required.
- Hands-on experience in RTL coding, verification, synthesis, timing exploration, equivalence check, etc.
- Domain understanding one of the interface standards: PCIe, USB, Display Port, Ethernet, or DDR
- Good communication skills while interacting with internal teams and customers.
Preferred Experience:
- Experience in Design Compiler, Fusion Compiler, Spyglass or VC Spyglass
- Experience in UVM methodology
- Experience in DesignWare Cores
- Experience in TCL, Perl, Python, or other shell scripting
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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