ASIC Physical Design, Engineer

We are looking for ASIC Physical Design Engineer to join our team.

In this role you will be responsible for digital implementation from RTL to GDS2, which includes the following stages:

• Gate level netlist synthesis
• Physical implementation
• Static Timing Analysis
• EMIR
• Physical verification
• Signoff

Key Qualifications

• Possesses relevant experience in deep submicron CMOS technologies and ASIC digital implementation
• Knowledge of the full design cycle from RTL to GDSII
• Good software and scripting skills, version control, understanding of CAD automation methods.
• Good written and verbal communication in English
• Teamwork or Network relation experiences
• Problem-solving and organizational skills
• Academic and practical exposure in the following fields: high-speed design, low-power design, high-speed clock design and distribution, timing closure, signal integrity
• Requires a degree in Electrical or Computer Engineering with specialization in Micro-electronics (or equivalent)

Preferred Experience

• 0+ years of relevant work experience.
• ASIC design methodology experience in back-end flows of digital and Mixed Signal circuit design.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned digital blocks, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.