Principal Engineer, CAD and Signal Integrity

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. 

In the System Solutions Group we are shaping solutions for dependable systems, requiring safety, security, reliability, low power and more. Our team works with customers and industry partners to understand their needs and identify technical requirements. We are passionate about methodologies and automation: we collaborate with customers to make their job easier when they develop their products.

Principal Engineer, CAD and Signal Integrity 

The role is for a Principal Engineer of IP/Subsystem/SoC Design in the System Solutions Group (SSG). At SSG, we are a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, methodology to enable our customers complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies.

As part of this role, you can expect to develop and deliver your expertise in advanced methodologies, technology, and flow implementations.  You’ll interface to SSG technical leaders to implement Signal and Power Integrity and packaging flow variations for some of the world’s most advanced technology suppliers. The role will expose you to various innovative technologies deployed for SIPI and advanced packaging for Semiconductors.

Qualifications
 

• Understand the SoC/IP Architecture and develop SoC/IP Flows and methodologies for SIPI and Advanced Packaging Architecture.
• Working knowledge of Ansys Multi-Physics tools and be able to script design flow around tools like HFSS, SiWave, Redhawk for EM-IR (both static and Dynamic), Redhawk for Thermal analysis
• Knowledge of PDN analysis and has generated CPM models and performed chip-package-PCB system simulations in both time and frequency domain.
• Good understanding of PCB, Packaging and RDL designs is required to be able to prepare design flows and methodologies.
• Work with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy packaging and signal integrity solutions.
• Ramp-up on new 3DIC packaging and SI tools and methodologies using Synopsys Products to enable customers.

Required

• Bachelors,MS/Phd in EE with 10+ years’ experience in ASIC implementation techniques and chip assembly methodologies.   Demonstration of technical leadership or previous management experience is highly recommended.
• Strong knowledge of Signal Integrity fundamentals (PDN, EMIR, Basic Analog circuits, T-Line theory, Xtalk, S-parameters, channel simulations)
• 2.5/3D packaging experience and knowledge of CoWoS, InFo, RDL… is a plus.
• Great technical documentation skills
• Good working knowledge of Unix/Linux environment.  Ability to run EDA tools in Unix through scripting language.
• In addition to the mentioned qualifications, candidates with a demonstrated ability to devise innovative design solutions will be highly valued.

The base salary range across the U.S. for this role is between $147,000 to $221,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on several job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request
 

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.